FOR IMMEDIATE RELEASE

For more information, contact:
Georgia Marszalek, Accellera, Public Relations Counsel, + 1 650 345 7477, georgia@valleypr.com
Karen McCabe, IEEE Marketing Manager, +1 732 562 3824, k.mccabe@ieee.org

Los Gatos, Calif., USA 15 January 2001--Accellera, the EDA organization resulting from the unification of Open Verilog International (OVI) and VHDL International (VI), and the IEEE today announced that the VITAL ASIC Modeling Specification for VHDL simulation has been approved by the IEEE-SA as a revised standard.

VITAL or IEEE 1076.4, an ASIC library design standard for IEEE 1076-1993 or the VHDL standard, adds modeling enhancements and addresses usability issues. VITAL accelerates the development of sign-off quality ASIC macrocell simulation libraries by leveraging existing model creation methodologies. It was developed by leading EDA and semiconductor companies, and was first accepted as an IEEE standard in 1995.

"Accellera collaborated with the IEEE, a leading international standards organization to demonstrate our commitment to enhance language-based design", noted Dennis Brophy, Accellera chairman, VITAL technical committee chairman and director of strategic business development at Model Technology, a Mentor Graphics Company. "VITAL-2000 users will find that the standard ASIC memory model improves memory modeling support and allows HDL simulators to run VITAL memory models faster."

About the Revised VITAL Standard
The major addition to VITAL is a standard ASIC memory model package. VITAL-2000 now specifies the IEEE 1076-1993 VHDL standard and the IEEE P1497 Standard Delay Format (SDF 4.0). The development of more accurate simulation models is supported with features that allow a model developer to ignore scheduling of default delays and scheduling of fast path delays.

In addition, due to shrinking semiconductor geometries, critical enhancements have been made to support more accurate delay simulation. These include support for multi-source interconnect delays, conditional delay selection, negative glitch and skew constraint checks.

Price and Availability
The VITAL ASIC Modeling Standard is available now from the IEEE for $75.00 (USD) or $60.00 (USD) for IEEE members. To order, visit www.ieee.org.

About Accellera
Accellera exists to drive worldwide development and the use of standards required by systems, semiconductor and design tools companies, which enhance a language-based design automation process. This includes support of technical groups involved with developing standards for IEEE 1364 or the Verilog hardware description language (HDL) and IEEE 1076 or VHDL.

Companies, organizations and individuals that would like to join Accellera or receive information can contact Accellera at 15466 Los Gatos Blvd., Suite 109-071, Los Gatos, CA 95032. (408) 358-9510 or via email at info@accellera.org or visit www.accellera.org.

Accellera sponsors the annual HDL Conference, February 28 through March 2, 2001 in Santa Clara, Calif. Visit www.hdlcon.org for information.

About the IEEE Standards Association
The IEEE Standards Association (IEEE-SA) is an international membership organization serving today's industries with a complete portfolio of standards programs. The IEEE-SA is a major contributor to the IEEE, which is the world's largest technical professional society. IEEE-SA membership, through its IEEE association, promotes the engineering process by creating, developing, integrating, sharing and applying knowledge about electro- and information technologies and sciences for the benefit of humanity and the profession. More information is found at http://standards.ieee.org/sa-mem/index.html.

Acronyms:

ASIC   Application Specific IC
EDA   Electronic Design Automation
HDL   Hardware Description Language
IC   Integrated Circuit
IEEE   Institute of Electrical and Electronic Engineers
IEEE 1076   IEEE VHDL standard
IEEE 1364   IEEE Verilog HDL standard
OVI   Open Verilog International
SDF   Standard Delay Format
VITAL   VHDL Initiative Towards ASIC Libraries
VHDL   VHSIC (Very High-Speed IC) HDL
VI   VHDL International